1. Field of the Invention
The present invention relates to a delay circuit, and more particularly to a delay circuit that includes a plurality of delay elements connected in series.
2. Description of Related Art
Semiconductor devices may have a delay circuit for adjusting the timing of a control signal inside. For example, Japanese Patent Application Laid-Open No. 2003-273712 describes an example of using inverters as delay elements, which are connected in series to constitute a delay circuit.
In the case of the delay circuit described in Japanese Patent Application Laid-Open No. 2003-273712, when an input signal changes from a low level to a high level, the odd-numbered inverters output a low level and the even-numbered inverters output a high level. Here, N-channel MOS transistors turn ON in the inverters that output the low level, and P-channel MOS transistors turn ON in the inverters that output the high level. Given 2N stages of inverters, the total delay time is N×Tp+N×Tn, where Tn is the time needed for an N-channel MOS transistor to pull down the inverter output, and Tp is the time needed for a P-channel MOS transistor to pull up the inverter output.
Since the driving capability of a transistor depends on temperature, voltage, and the like, the foregoing values Tn and Tp also vary with temperature and voltage. As a result, the delay time of the entire delay circuit varies with temperature, voltage, etc. Variations in the delay time of the entire delay circuit due to changes in temperature, voltage, and the like include both the variation components of Tn and the variation components of Tp. It is therefore not easy to evaluate variations in the delay time of the entire delay circuit.
For example, a state where the N-channel MOS transistors have a low threshold voltage (perform switching at high speed) will be referred to as nL, and a state where the N-channel MOS transistors have a high threshold voltage (perform switching at low speed) will be referred to as nH. A state where the P-channel MOS transistors have a low threshold voltage (perform switching at high speed) will be referred to as pL, and a state where the P-channel MOS transistors have a high threshold voltage (perform switching at low speed) will be referred to as pH. There are four possible cases of variations in the delay time of the entire delay circuit, including nLpL, nLpH, nHpL, and nHpH.
Consequently, if the output signal of the delay circuit needs to be activated in synchronization with the operation timing of a predetermined circuit, it is difficult to make a change in operation timing occurring in the predetermined circuit due to variations in temperature, voltage, and the like coincide with a change in delay time occurring in the delay circuit due to variations in temperature, voltage, etc.